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Independent analysis from Chips and Cheese examines Intel's Lion Cove P-core architecture in gaming workloads, finding strong single-threaded performance but revealing memory latency challenges that affect real-world gaming scenarios.
Hardware engineer Andrew Zonenberg published detailed documentation of undisclosed register interfaces and configuration options in Microchip's VSC8512 12-port Gigabit Ethernet PHY, revealing capabilities hidden behind NDA-restricted documentation.
Technical analysis of Nvidia's Blackwell B200 GPU architecture reveals 208 billion transistors, 192 streaming multiprocessors, and 8 TB/s memory bandwidth, representing a significant leap in AI accelerator design.
The field-programmable gate array celebrates its 40th anniversary in 2025, marking four decades since Xilinx co-founders Ross Freeman and Bernard Vonderschmitt introduced the XC2064, the first commercially viable FPGA, in 1985.
AMD revealed details of its next-generation EPYC Venice server processors featuring up to 256 Zen 6 cores, targeting 2026 availability for data center and high-performance computing workloads.
Apple announced at WWDC 2025 that macOS Tahoe will be the final release supporting Intel-based Macs, with macOS 27 requiring Apple Silicon and Rosetta 2 translation entering a phased deprecation.
Lawrence Livermore National Laboratory's El Capitan exascale supercomputer begins integrating AI capabilities with traditional physics simulations for nuclear stockpile stewardship, marking a shift in how national laboratories approach computational science.
UC Santa Barbara's OpenTPU project, an open-source reimplementation of Google's Tensor Processing Unit architecture, resurfaces on developer forums as interest in custom AI accelerator designs continues to grow.
A VideoLAN developer submitted a merge request to optimize memory alignment in the dav1d AV1 decoder, reducing struct sizes by 264 bytes and claiming approximately 3% performance improvement for 1080p video decoding.
Lin Nan, a former head scientist at Dutch lithography equipment maker ASML, is leading research efforts at a Chinese institution working on extreme ultraviolet lithography technology, according to South China Morning Post reporting.
Nvidia CEO Jensen Huang arrived in Beijing on April 17, 2025, for an unannounced visit as the company navigates US export restrictions that have limited its ability to sell advanced AI chips to Chinese customers.
Researchers at CERN's AEgIS experiment demonstrated that commercial smartphone camera sensors can detect antimatter particles with unprecedented spatial resolution, offering a low-cost alternative to specialized scientific detectors.
SoftBank Group announced an all-cash acquisition of Ampere Computing for $6.5 billion, bringing the Arm-based server chip designer under the same corporate umbrella as Arm Holdings itself.
Google X's Taara project announced a next-generation silicon photonic chip capable of transmitting 10 Gbps over 1 kilometer using beams of light, marking a shift from mechanical to solid-state beam steering for wireless optical communications.
SpaceX conducted its eighth integrated flight test of the Starship vehicle on March 6, 2025, with the upper stage experiencing attitude control issues that prevented the planned booster catch attempt and led to vehicle breakup over the Atlantic Ocean.
Apple announced the iPhone 16e on February 19, 2025, featuring the C1, the company's first in-house cellular modem, marking a significant step toward reducing its dependence on Qualcomm for 5G connectivity.
Microsoft has removed Intel 8th, 9th, and 10th generation processors from the official Windows 11 24H2 CPU support list for new OEM systems, a decision that appears connected to Intel's December 2024 transition of older integrated graphics to legacy support status.
The semiconductor industry's migration from monolithic SoCs to chiplet-based designs is creating unprecedented complexity in chip architecture, driven by economics and the physical limits of traditional scaling.
IBM announced a breakthrough in 2nm chip manufacturing featuring vertical transistor stacking, promising higher density and efficiency for next-generation computing.
EXECUTIVE BRIEF Taiwan Semiconductor Manufacturing Company (TSMC) announced on January 17, 2025, a breakthrough 1.6-nanometer (nm) semiconductor manufacturing process featuring proprietary Quantum Tunneling Control (QTC) technology. The new process node, designated A16, represents a significant advancement beyond the company's current 2nm technolog…
EXECUTIVE BRIEF Samsung Electronics announced a significant breakthrough in 2-nanometer (2nm) semiconductor manufacturing technology on January 5, 2025. The company revealed its new Gate-All-Around Field Effect Transistor (GAAFET) architecture with enhanced multi-bridge channel design, which enables 30% improved power efficiency and 15% performance…
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